1. Field of the Invention
This invention concerns a circuit configuration with a temperature-dependent semiconductor component test and repair logic circuit, in which at least one temperature sensor is provided in a semiconductor chip having a semiconductor component.
Before being delivered to customers, semiconductor components, such as semiconductor memories, are tested as to whether they still operate properly at specific temperatures. This was previously done by placing a semiconductor memory in a tester in which the temperature applied to the semiconductor memory can be set externally. As soon as this temperature, for example 87.degree. C. is attained, the semiconductor memory in the tester is tested for its functionality through the application of specific test signals applied to it.
If the temperature in the tester cannot be regulated, the test results are often unsatisfactory because certain characteristics of a semiconductor memory are strongly dependent on the temperature. The possibility therefore definitely exists that at the test temperature, for example above 87.degree. C., it is not possible to detect reliably every possible defect in the semiconductor memory.
From the IEEE article "TRANSACTION ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS", Vol. 5, No. 3, September 1997, pp 270-276, CMOS sensors are known which consist of MOS circuits and which can be installed in integrated circuits for recording temperature. This publication does not, however, deal with the testing of memories.
Finally, Published, Non-Prosecuted German Patent Application DE 198 28 192 A1 discloses a circuit configuration for controlling the chip temperature of a semiconductor memory to be measured, in which circuit configuration at least one temperature sensor is provided in the chip having the semiconductor memory. In the chip, the semiconductor memory and the temperature sensor are connected with a temperature control unit. This enables a chip temperature of the semiconductor memory to be set to different values so that good test coverage can be achieved even if particular characteristics of the semiconductor memory are strongly dependent on temperature.
However, this prior art circuit configuration does not make possible the immediate repair of the semiconductor memory in the process of being tested. On the contrary, a repair of the semiconductor memory cannot be performed until the test has been completed, which repair can be carried out, for example, using normal laser fuses which are blown in the semiconductor memory according to the defective sites located during the test.
Another possibility consists therein, that a semiconductor memory is tested and repaired at every start-up of the semiconductor memory by a test and repair logic circuit provided on the chip. In other words, the repair is carried out directly on the chip having the semiconductor memory. A procedure of this kind can, however, deliver unsatisfactory results because in this case the semiconductor memory is not tested at the respective operating temperature required.